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? semiconductor components industries, llc, 2010 june, 2010 ? rev. 1 1 publication order number: nlsx5012/d nlsx5012 2-bit 100 mb/s configurable dual-supply level translator the nlsx5012 is a 2-bit configurable dual-supply autosensing bidirectional level translator that does not require a direction control pin. the i/o v cc - and i/o v l -ports are designed to track two different power supply rails, v cc and v l respectively. both the v cc and the v l supply rails are configurable from 0.9 v to 4.5 v. this allows a logic signal on the v l side to be translated to either a higher or a lower logic signal voltage on the v cc side, and vice-versa. the nlsx5012 offers the feature that the values of the v cc and v l supplies are independent. design flexibility is maximized because v l can be set to a value either greater than or less than the v cc supply. in contrast, the majority of competitive auto sense translators have a restriction that the value of the v l supply must be equal to less than (v cc - 0.4) v. the nlsx5012 has high output current capability, which allows the translator to drive high capacitive loads such as most high frequency emi filters. another feature of the nlsx5012 is that each i/o_v ln and i/o_v ccn channel can function as either an input or an output. an output enable (en) input is available to reduce the power consumption. the en pin can be used to disable both i/o ports by putting them in 3-state which significantly reduces the supply current from both v cc and v l . the en signal is referenced to the v l supply. features ? wide v cc , v l operating range: 0.9 v to 4.5 v ? v l and v cc are independent ? v l may be greater than, equal to, or less than v cc ? high 100 pf capacitive drive capability ? high ? speed with 140 mb/s guaranteed date rate for v cc , v l > 1.8 v ? low bit ? to ? bit skew ? overvoltage tolerant enable and i/o pins ? non ? preferential power ? up sequencing ? power ? off protection ? small packaging: udfn8, so ? 8, micro8 ? these are pb ? free devices typical applications ? mobile phones, pdas, other portable devices important information ? esd protection for all pins: ? hbm (human body model) > 8000 v http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. udfn8 mu suffix case 517aj 1 8 va = specific device code m = date code = pb ? free package ae m 1 8 so ? 8 d suffix case 751 a = assembly location y = year w = work week = pb ? free package sx5012 alyw 1 8 micro8 dm suffix case 846a 1 5012 ayw 1 8 a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagrams device package shipping ? ordering information nlsx5012mutag udfn8 (pb ? free) 3000/t ape & reel nlsx5012dr2g so ? 8 (pb ? free) 2500/t ape & reel NLSX5012DMR2G micro8 (pb ? free) 4000/t ape & reel
nlsx5012 http://onsemi.com 2 figure 1. t ypical application circuit i/o v l 1 i/o v l n en oe i/on i/o1 gnd +1.8 v system +1.8v +3.6v +3.6 v system i/on i/o1 gnd gnd nlsx5012 i/o v cc 1 i/o v cc n v l v cc figure 2. simplified functional diagram (1 i/o line) p one ? shot n one ? shot p one ? shot n one ? shot v l i/o v l i/o v cc v cc r1 r2 figure 3. application example for v l < v cc en ano c 2.5 v 3.0 v peripheral gnd nlsx5012 v l v cc i/o v l 2 i/o v cc 2 rx tx i/o v l 1 i/o v cc 1 tx rx figure 4. application example for v l > v cc en ano c 2.5 v 1.8 v peripheral gnd nlsx5012 v l v cc i/o v l 2 i/o v cc 2 rx tx i/o v l 1 i/o v cc 1 tx rx
nlsx5012 http://onsemi.com 3 figure 5. logic diagram v l v cc gnd en i/o v l 1 i/o v l 2 i/o v cc 1 i/o v cc 2 figure 6. pin assignments micro8 (top view) 1 2 3 4 8 7 6 5 1 8 2 3 4 7 6 5 soic ? 8 (top view) udfn8 (top view) v cc i/o v cc 1 i/o v cc 2 en v l i/o v l 1 i/o v l 2 gnd 8 7 6 5 1 2 3 4 v cc i/o v cc 1 i/o v cc 2 en v l i/o v l 1 i/o v l 2 gnd v cc i/o v cc 1 i/o v cc 2 en v l i/o v l 1 i/o v l 2 gnd pin assignment pins description v cc v cc input v oltage v l v l input v oltage gnd ground en output enable i/o v cc n i/o port, referenced to v cc i/o v l n i/o port, referenced to v l function table en operating mode l hi ? z h i/o buses connected
nlsx5012 http://onsemi.com 4 maximum ratings symbol parameter value condition unit v cc high ? side dc supply v oltage ? 0.5 to +5.5 v v l low ? side dc supply v oltage ? 0.5 to +5.5 v i/o v cc v cc ? referenced dc input/output v oltage ? 0.5 to +5.5 v i/o v l v l ? referenced dc input/output v oltage ? 0.5 to +5.5 v v i enable control pin dc input v oltage ? 0.5 to +5.5 v i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i cc dc supply current through v cc 100 ma i l dc supply current through v l 100 ma i gnd dc ground current through ground pin 100 ma t stg storage t emperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. recommended opera ting conditions symbol parameter min max unit v cc high ? side positive dc supply voltage 0.9 4.5 v v l low ? side positive dc supply v oltage 0.9 4.5 v v i enable control pin v oltage gnd 4.5 v v io bus input/output v oltage i/o v cc i/o v l gnd gnd 4.5 4.5 v t a operating temperature range ? 40 +85 c t/ v input transition rise or rate v i , v io from 30% to 70% of v cc ; v cc = 3.3 v 0.3 v 0 10 ns
nlsx5012 http://onsemi.com 5 dc electrical characteristics symbol parameter test conditions (note 1) v cc (v) (note 2) v l (v) (note 3) ? 40 c to +85 c ? 55 c to +125 c unit min typ (note 4) max min max v ihc i/o v cc input high voltage 0.9 ? 4.5 0.9 ? 4.5 2/3 * v cc ? ? 2/3 * v cc ? v v ilc i/o v cc input low v oltage 0.9 ? 4.5 0.9 ? 4.5 ? ? 1/3 * v cc ? 1/3 * v cc v v ihl i/o v l input high voltage 0.9 ? 4.5 0.9 ? 4.5 2/3 * v l ? ? 2/3 * v l ? v v ill i/o v l input low v oltage 0.9 ? 4.5 0.9 ? 4.5 ? ? 1/3 * v l ? 1/3 * v l v v ih control pin input high voltage t a = +25 c 0.9 ? 4.5 0.9 ? 4.5 2/3 * v l ? ? 2/3 * v l ? v v il control pin input low voltage t a = +25 c 0.9 ? 4.5 0.9 ? 4.5 ? ? 1/3 * v l ? 1/3 * v l v v ohc i/o v cc output high voltage i/o v cc source current = 20 a 0.9 ? 4.5 0.9 ? 4.5 0.9 * v cc ? ? 0.9 * v cc ? v v olc i/o v cc output low voltage i/o v cc sink current = 20 a 0.9 ? 4.5 0.9 ? 4.5 ? ? 0.2 ? 0.2 v v ohl i/o v l output high voltage i/o v l source current = 20 a 0.9 ? 4.5 0.9 ? 4.5 0.9 * v l ? ? 0.9 * v l ? v v oll i/o v l output low voltage i/o v l sink current = 20 a 0.9 ? 4.5 0.9 ? 4.5 ? ? 0.2 ? 0.2 v i qvcc v cc supply current en = v l , i o = 0 a, (i/o v cc = 0 v or v cc , i/o v l = float) or (i/o v cc = float, i/o v l = 0 v or v l ) 0.9 ? 4.5 0.9 ? 4.5 ? ? 1 ? 2.5 a i qvl v l supply current 0.9 ? 4.5 0.9 ? 4.5 ? ? 1 ? 2.5 a i ts ? vcc v cc tristate output mode supply current t a = +25 c, en = 0 v (i/o v cc = 0 v or v cc , i/o v l = float) or (i/o v cc = float, i/o v l = 0 v or v l ) 0.9 ? 4.5 0.9 ? 4.5 ? ? 0.5 ? 1.5 a i ts ? vl v l tristate output mode supply current 0.9 ? 4.5 0.9 ? 4.5 ? ? 0.5 ? 1.5 a i oz i/o tristate output mode leakage current t a = +25 c, en = 0v 0.9 ? 4.5 0.9 ? 4.5 ? ? 1 ? 1.5 a i i control pin input current t a = +25 c 0.9 ? 4.5 0.9 ? 4.5 ? ? 1 ? 1 a i off power off leakage current i/o v cc = 0 to 4.5v, 0 0 ? ? 1 ? 1.5 a i/o v l = 0 to 4.5 v 0.9 ? 4.5 0 ? ? 1 ? 1.5 0 0.9 ? 4.5 ? ? 1 ? 1.5 1. normal test conditions are v i = 0 v, c iovcc 15 pf and c iovl 15 pf, unless otherwise specified. 2. v cc is the supply voltage associated with the i/o v cc port, and v cc ranges from +0.9 v to 4.5 v under normal operating conditions. 3. v l is the supply voltage associated with the i/o v l port, and v l ranges from +0.9 v to 4.5 v under normal operating conditions. 4. typical values are for v cc = +2.8 v, v l = +1.8 v and t a = +25 c. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design.
nlsx5012 http://onsemi.com 6 timing characteristics symbol parameter test conditions (note 5) v cc (v) (note 6) v l (v) (note 7) ? 55 c to +125 c unit min typ (note 8) max t r ? vcc i/o v cc rise time c iovcc = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 8.5 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 3.5 t f ? vcc i/o v cc fall time c iovcc = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 8.5 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 3.5 t r ? vl i/o v l rise time c iovl = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 8.5 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 3.5 t f ? vl i/o v l fall time c iovl = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 8.5 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 3.5 z ovcc i/o v cc one ? shot output impedance (note 9) 0.9 1.8 4.5 0.9 ? 4.5 ? ? ? 37 20 6.0 ? ? ? z ovl i/o v l one ? shot out- put impedance (note 9) 0.9 1.8 4.5 0.9 ? 4.5 ? ? ? 37 20 6.0 ? ? ? t pd_vl ? vcc propagation delay (driving i/o v cc ) c iovcc = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 35 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 10 c iovcc = 30 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 35 1.8 ? 4.5 1.8 ? 4.5 ? ? 10 c iovcc = 50 pf 1.0 ? 4.5 1.0 ? 4.5 ? ? 37 1.8 ? 4.5 1.8 ? 4.5 ? ? 11 c iovcc = 100 pf 1.2 ? 4.5 1.2 ? 4.5 ? ? 40 1.8 ? 4.5 1.8 ? 4.5 ? ? 13 t pd_vcc ? vl propagation delay (driving i/o v l ) c iovl = 15 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 35 ns 1.8 ? 4.5 1.8 ? 4.5 ? ? 10 c iovl = 30 pf 0.9 ? 4.5 0.9 ? 4.5 ? ? 35 1.8 ? 4.5 1.8 ? 4.5 ? ? 10 c iovl = 50 pf 1.0 ? 4.5 1.0 ? 4.5 ? ? 37 1.8 ? 4.5 1.8 ? 4.5 ? ? 11 c iovl = 100 pf 1.2 ? 4.5 1.2 ? 4.5 ? ? 40 1.8 ? 4.5 1.8 ? 4.5 ? ? 13 t sk channel ? to ? channel skew c iovcc = 15 pf, c iovl = 15 pf (note 9) 0.9 ? 4.5 0.9 ? 4.5 ? ? 0.15 ns i in_peak input driver maximum peak current en = v l ; i/o_v cc = 1 mhz square w ave, amplitude = v cc , or i/o_v l = 1 mhz square w ave, amplitude = v l (note 9) 0.9 ? 4.5 0.9 ? 4.5 ? ? 5.0 ma 5. normal test conditions are v i = 0 v, c iovcc 15 pf and c iovl 15 pf, unless otherwise specified. 6. v cc is the supply voltage associated with the i/o v cc port, and v cc ranges from +0.9 v to 4.5 v under normal operating conditions. 7. v l is the supply voltage associated with the i/o v l port, and v l ranges from +0.9 v to 4.5 v under normal operating conditions. 8. typical values are for v cc = +2.8 v, v l = +1.8 v and t a = +25 c. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design. 9. guaranteed by design.
nlsx5012 http://onsemi.com 7 timing characteristics (continued) symbol parameter test conditions (note 10) v cc (v) (note 11) v l (v) (note 12) ? 55 c to +125 c unit min typ (note 13) max t en ? vcc i/o_v cc output enable time t pzh c iovcc = 15 pf, i/o_v l = v l 0.9 ? 4.5 0.9 ? 4.5 ? ? 160 ns t pzl c iovcc = 15 pf, i/o_v l = 0 v 0.9 ? 4.5 0.9 ? 4.5 ? ? 130 t en ? vl i/o_v l output enable time t pzh c iovl = 15 pf, i/o_v cc = v cc 0.9 ? 4.5 0.9 ? 4.5 ? ? 160 ns t pzl c iovl = 15 pf, i/o_v cc = 0 v 0.9 ? 4.5 0.9 ? 4.5 ? ? 130 t dis ? vcc i/o_v cc output disable time t phz c iovcc = 15 pf, i/o_v l = v l 0.9 ? 4.5 0.9 ? 4.5 ? ? 210 ns t plz c iovcc = 15 pf, i/o_v l = 0 v 0.9 ? 4.5 0.9 ? 4.5 ? ? 175 t dis ? vl i/o_v l output disable time t phz c iovl = 15 pf, i/o_v cc = v cc 0.9 ? 4.5 0.9 ? 4.5 ? ? 210 ns t plz c iovl = 15 pf, i/o_v cc = 0 v 0.9 ? 4.5 0.9 ? 4.5 ? ? 175 mdr maximum data rate c io = 15 pf 0.9 ? 4.5 0.9 ? 4.5 50 ? ? mbps 1.8 ? 4.5 1.8 ? 4.5 140 ? ? c io = 30 pf 0.9 ? 4.5 0.9 ? 4.5 40 ? ? 1.8 ? 4.5 1.8 ? 4.5 120 ? ? c io = 50 pf 1.0 ? 4.5 1.0 ? 4.5 30 ? ? 1.8 ? 4.5 1.8 ? 4.5 100 ? ? c io = 100 pf 1.2 ? 4.5 1.2 ? 4.5 20 ? ? 1.8 ? 4.5 1.8 ? 4.5 60 ? ? 10. normal test conditions are v i = 0 v, c iovcc 15 pf and c iovl 15 pf, unless otherwise specified. 11. v cc is the supply voltage associated with the i/o v cc port, and v cc ranges from +0.9 v to 4.5 v under normal operating conditions. 12. v l is the supply voltage associated with the i/o v l port, and v l ranges from +0.9 v to 4.5 v under normal operating conditions. 13. typical values are for v cc = +2.8 v, v l = +1.8 v and t a = +25 c. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design.
nlsx5012 http://onsemi.com 8 dynamic power consumption (t a = +25 c) symbol parameter test conditions v cc (v) (note 14) v l (v) (note 15) typ (note 16) unit c pd_vl v l = input port, v cc = output port c load = 0, f = 1 mhz, en = v l (outputs enabled) 0.9 4.5 39 pf 1.5 1.8 20 1.8 1.5 17 1.8 1.8 14 1.8 2.8 13 2.5 2.5 14 2.8 1.8 13 4.5 0.9 19 v cc = input port, v l = output port c load = 0, f = 1 mhz, en = v l (outputs enabled) 0.9 4.5 37 pf 1.5 1.8 30 1.8 1.5 29 1.8 1.8 29 1.8 2.8 29 2.5 2.5 30 2.8 1.8 29 4.5 0.9 19 c pd_vcc v l = input port, v cc = output port c load = 0, f = 1 mhz, en = v l (outputs enabled) 0.9 4.5 29 pf 1.5 1.8 29 1.8 1.5 29 1.8 1.8 29 1.8 2.8 29 2.5 2.5 30 2.8 1.8 29 4.5 0.9 35 v cc = input port, v l = output port c load = 0, f = 1 mhz, en = v l (outputs enabled) 0.9 4.5 21 pf 1.5 1.8 18 1.8 1.5 18 1.8 1.8 14 1.8 2.8 13 2.5 2.5 14 2.8 1.8 13 4.5 0.9 30 14. v cc is the supply voltage associated with the i/o v cc port, and v cc ranges from +0.9 v to 4.5 v under normal operating conditions. 15. v l is the supply voltage associated with the i/o v l port, and v l ranges from +0.9 v to 4.5 v under normal operating conditions. 16. typical values are at t a = +25 c. 17. c pd vl and c pd vcc are defined as the value of the ic?s equivalent capacitance from which the operating current can be calculated for the v l and v cc power supplies, respectively. i cc = i cc (dynamic) + i cc (static) i cc (operating) c pd x v cc x f in x n sw where i cc = i cc_vcc + i cc vl and n sw = total number of outputs switching.
nlsx5012 http://onsemi.com 9 static power consumption (t a = +25 c) symbol parameter test conditions v cc (v) (note 18) v l (v) (note 19) typ (note 20) unit c pd_vl v l = input port, v cc = output port c load = 0, f = 1 mhz, en = gnd (outputs disabled) 0.9 4.5 0.01 pf 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 v cc = input port, v l = output port c load = 0, f = 1 mhz, en = gnd (outputs disabled) 0.9 4.5 0.01 pf 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 c pd_vcc v l = input port, v cc = output port c load = 0, f = 1 mhz, en = gnd (outputs disabled) 0.9 4.5 0.01 pf 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 v cc = input port, v l = output port c load = 0, f = 1 mhz, en = gnd (outputs disabled) 0.9 4.5 0.01 pf 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 18. v cc is the supply voltage associated with the i/o v cc port, and v cc ranges from +0.9 v to 4.5 v under normal operating conditions. 19. v l is the supply voltage associated with the i/o v l port, and v l ranges from +0.9 v to 4.5 v under normal operating conditions. 20. typical values are at t a = +25 c
nlsx5012 http://onsemi.com 10 nlsx5012 en i/o v l v l v cc c iovcc t rise/fall 3 ns i/o v l i/o v cc t pd_vl ? vcc 90% 50% 10% 90% 50% 10% t pd_vl ? vcc t f ? vcc t r ? vcc figure 7. driving i/o v l test circuit and timing i/o v cc nlsx5012 en i/o v l v l v cc c iovl source t rise/fall 3 ns i/o v cc i/o v l t pd_vcc ? vl 90% 50% 10% 90% 50% 10% t pd_vcc ? vl t f ? vl t r ? vl figure 8. driving i/o v cc test circuit and timing i/o v cc source open pulse generator r t dut v cc r l r 1 c l 2xv cc test switch t pzh , t phz open t pzl , t plz 2 x v cc c l = 15 pf or equivalent (includes jig and probe capacitance) r l = r 1 = 50 k or equivalent r t = z out of pulse generator (typically 50 ) figure 9. test circuit for enable/disable time measurement v cc gnd t f t r 10% 50% 90% 10% 50% 90% t r t plh t phl t f 50% 50% 90% 10% t pzl t plz t pzh t phz gnd high impedance v ol v oh high impedance figure 10. timing definitions for propagation delays and enable/disable measurement en input 50% v l output output output
nlsx5012 http://onsemi.com 11 important applications information level translator architecture the nlsx5012 auto ? sense translator provides bi ? directional logic voltage level shifting to transfer data in multiple supply voltage systems. these level translators have two supply voltages, v l and v cc , which set the logic levels on the input and output sides of the translator. when used to transfer data from the i/o v l to the i/o v cc ports, input signals referenced to the v l supply are translated to output signals with a logic level matched to v cc . in a similar manner, the i/o v cc to i/o v l translation shifts input signals with a logic level compatible to v cc to an output signal matched to v l . the nlsx5012 translator consists of bi ? directional channels that independently determine the direction of the data flow without requiring a directional pin. one ? shot circuits are used to detect the rising or falling input signals. in addition, the one ? shots decrease the rise and fall times of the output signal for high ? to ? low and low ? to ? high transitions. input driver requirements auto ? sense translators such as the nlsx5012 have a wide bandwidth, but a relatively small dc output current rating. the high bandwidth of the bi ? directional i/o circuit is used to quickly transform from an input to an output driver and vice versa. the i/o ports have a modest dc current output specification so that the output driver can be over driven when data is sent in the opposite direction. for proper operation, the input driver to the auto ? sense translator should be capable of driving 2 ma of peak output current. the bi ? directional configuration of the translator results in both input stages being active for a very short time period. although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard cmos input stage. enable input (en) the nlsx5012 translator has an enable pin (en) that provides tri ? state operation at the i/o pins. driving the enable pin to a low logic level minimizes the power consumption of the device and drives the i/o v cc and i/o v l pins to a high impedance state. normal translation operation occurs when the en pin is equal to a logic high signal. the en pin is referenced to the v l supply and has over ? voltage tolerant (ovt) protection. uni ? directional versus bi ? directional t ranslation the nlsx5012 translator can function as a non ? inverting uni ? directional translator. one advantage of using the translator as a uni ? directional device is that each i/o pin can be configured as either an input or output. the configurable input or output feature is especially useful in applications such as spi that use multiple uni ? directional i/o lines to send data to and from a device. the flexible i/o port of the auto sense translator simplifies the trace connections on the pcb. power supply guidelines the values of the v l and v cc supplies can be set to anywhere between 0.9 and 4.5 v. design flexibility is maximized because v l may be either greater than or less than the v cc supply. in contrast, the majority of the competitive auto sense translators has a restriction that the value of the v l supply must be equal to less than (v cc ? 0.4) v. the sequencing of the power supplies will not damage the device during power ? up operation. in addition, the i/o v cc and i/o v l pins are in the high impedance state if either supply voltage is equal to 0 v. for optimal performance, 0.01 to 0.1 f decoupling capacitors should be used on the v l and v cc power supply pins. ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the pcb. the noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the pcb connection traces. the nlsx5012 translators have a power down feature that provides design flexibility. the output ports are disabled when either power supply is off (v l or v cc = 0 v). this feature causes all of the i/o pins to be in the power saving high impedance state.
nlsx5012 http://onsemi.com 12 package dimensions udfn8 1.8 x 1.2, 0.4p case 517aj ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. mold flash allowed on terminals along edge of package. flash may not exceed 0.03 onto bottom surface of terminals. 5. detail a shows optional construction for terminals. ?? a b e d bottom view b e 8x b a c c note 3 0.10 c pin one reference top view 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 1 4 5 8 dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.127 ref b 0.15 0.25 d 1.80 bsc e 1.20 bsc e 0.40 bsc l 0.45 0.55 e/2 b2 0.30 ref l1 0.00 0.03 l2 0.40 ref detail a (l2) (b2) note 5 l1 detail a m 0.10 m 0.05 0.22 0.32 8x 1.50 0.40 pitch 0.66 dimensions: millimeters mounting footprint 7x 1 soldermask defined
nlsx5012 http://onsemi.com 13 package dimensions so ? 8 case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint*
nlsx5012 http://onsemi.com 14 package dimensions micro8 case 846a ? 02 issue h s b m 0.08 (0.003) a s t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. b e pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane a a1 c l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 8x 8x 6x mm inches scale 8:1 1.04 0.041 0.38 0.015 5.28 0.208 4.24 0.167 3.20 0.126 0.65 0.0256 dim a min nom max min millimeters ?? ?? 1.10 ?? inches a1 0.05 0.08 0.15 0.002 b 0.25 0.33 0.40 0.010 c 0.13 0.18 0.23 0.005 d 2.90 3.00 3.10 0.114 e 2.90 3.00 3.10 0.114 e 0.65 bsc l 0.40 0.55 0.70 0.016 ?? 0.043 0.003 0.006 0.013 0.016 0.007 0.009 0.118 0.122 0.118 0.122 0.026 bsc 0.021 0.028 nom max 4.75 4.90 5.05 0.187 0.193 0.199 h e h e d d e on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nlsx5012/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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